Risk-V — 5-Stage Pipelined RISC-V Microarchitecture Study
A structural, visual microarchitecture study of a complete 5-stage pipelined RISC-V RV32I processor built entirely from fundamental digital logic primitives in Logisim-evolution. Every component is visible and simulatable at the gate level, with full hazard detection, operand forwarding, branch prediction, and a 14-suite automated test framework. Includes comprehensive MkDocs documentation with detailed theory on pipeline hazards and forwarding.
Jul 5, 2026